1. Field of the Invention
The present invention relates to a semiconductor device fabrication method, and more particularly, to a method of fabricating a capacitor.
2. Background of the Related Art
In order to increase the integration of semiconductor devices, such as DRAMs, attempts have been made to decrease the size of capacitors and transistors. However, decreasing the size of the capacitor results in decreased capacitance, and an excessive decrease of the capacitance can cause a DRAM to fail. Accordingly, several methods have been considered to increase the capacitance of a capacitor while still decreasing an area of a semiconductor substrate required to form the capacitor.
One method is to transform a capacitor into a three-dimensional shape, to increase the surface area of the capacitor electrodes, thereby increasing its capacitance. A background art fabrication method of a capacitor having a three-dimensional electrode will now be described with reference to FIGS. 1A-1E.
As shown in FIG. 1A, a semiconductor substrate 100 is doped with impurities to form a plurality of conductive regions 101. An interlayer insulation film 102 is formed on the semiconductor substrate 100. The interlayer insulation film 102 is etched to form contact holes 103 through the interlayer insulation film 102 at positions corresponding to the conductive regions 101. The contact holes 103 are filled with plugs 104 formed of a conductive material. Then, a barrier metal layer 105 is formed on upper surfaces of the plugs 104 and the interlayer insulation film 102.
As further shown in FIG. 1B, a first conductive film 106 is formed on the barrier metal layer 105. A mask pattern 107 is formed on the first conductive film 106 at positions corresponding to the conductive plugs 104 and so that the elements of the mask pattern 107 are as large as the conductive plugs 104. The mask pattern 107 has a high etching selectivity against the first conductive film 106.
Referring to FIG. 1C, a second conductive film (not shown) formed of the same material as the first conductive film 106 is formed on the entire structure, and an anisotropical etching is carried out to obtain conductive side wall spacers 108 on each side wall of the elements of the mask pattern 107. Then, the first conductive layer 106 is patterned, using the mask pattern 107 and the sidewall spacers 108 as a mask, to form a first conductive layer pattern 106'.
In FIG. 1D, the mask pattern 107 is removed to obtain a lower electrode 109 including the first conductive pattern 106' and the side wall spacers 108, which are shaped like horns on upper surface edge portions of the first conductive pattern 106'.
Then, as shown in FIG. 1E, a dielectric layer 110 and a third conductive layer (an upper electrode for the capacitor) 111 are sequentially formed on and along the outer surface of the lower electrode 109, thereby completing the capacitor fabrication.
Although the background art process results in a capacitor having three dimensional electrodes, which increases the capacitance of the device, the structure has several drawbacks. First, the height of the electrodes leads to significant irregularity along an upper surface of the semiconductor substrate. As a result, it becomes difficult to apply a micro-processing to films on such a rugged surface. Further, since the thickness of a film disposed on such an irregular surface can vary, electrical characteristics of the semiconductor device can be uneven. In the worst case, a short may occur at a stepped portion of such a film due to the irregular surface. The end result is a decrease in the reliability of a semiconductor device.
Another way to increase the capacitance of a capacitor is to use a dielectric layer material having a high permitivity. A dielectric layer generally adapted to a DRAM capacitor is usually formed as a silicon oxide layer or a nitride layer. The capacitance of a capacitor can be increased by replacing such a dielectric layer with a ferro electric material having high permitivity, such as (Ba,Sr)TiO.sub.3, or Pb(Zr,Ti)O.sub.3. However, when ferro electrics such as (Ba,Sr)TiO.sub.3 or Pb(Zr,Ti)O.sub.3 are used as a dielectric material layer, the material forming the lower electrode and the oxygen included in the ferro electric material tend to react at a high temperature, and an oxide film is formed on the surface of the lower electrode. To avoid this problem, studies are being conducted; wherein a material such as Pt which does not tend to oxidize, or a conductive film formed of materials such as Ru and Ir, which oxidize, but form a conductive oxide layer, are employed as the material for a lower electrode for the capacitor.
Unfortunately, it is difficult to use Pt, Ru, or Ir as a lower electrode for a capacitor because these materials are not easily etched. As a result, it is difficult to process these materials into the fine shapes required in highly integrated circuit devices.
Also, since the etching selectivity of such materials is not high with regard to a photoresist used as a mask during the etching, the photoresist must be formed in relatively thick layers. An excessively thick photoresist film makes it very difficult to form fine shapes using presently available photolithography techniques.
In addition, if an etching process is carried out according to a physical operation, the material adapted for a lower electrode of a capacitor may become deposited on a photoresist or sidewalls of the etched lower electrode, so that when the etching is completed, a thin film remains around the lower electrode, even after removing the photoresist, thereby deteriorating reliability of a semiconductor device.